The present disclosure herein relates to semiconductor packages. It is a trend of the electronics industry to inexpensively fabricate lighter, smaller, faster, more multi-functional, higher performance, and higher reliability electronic products. A package technique used to fabricate such products may be an important technique for achieving this trend. A chip scale package (CSP) technique may provide a relatively small semiconductor package of a semiconductor chip scale.
High capacity of the semiconductor packages is also being demanded along with the small size of the semiconductor packages. Techniques capable of integrating many cells in a limited area of a semiconductor chip may be used to increase a memory capacity of a semiconductor package. These techniques, however, may need a high level precision for accurate and fine widths and spaces. Thus, research has been conducted for methods of realizing high integration of semiconductor packages using recently developed semiconductor chips or semiconductor packages, for example, a multi-chip stacked package including three-dimensionally stacked semiconductor chips or a stack type semiconductor package including three-dimensionally stacked semiconductor packages.